A parallel plate type (capacitively coupled) plasma processing apparatus, an inductively coupled plasma processing apparatus, a microwave plasma processing apparatus or the like has been widely used for performing a microprocess such as an etching process or a film forming process on a target object such as a semiconductor wafer (hereinafter, referred to as “wafer”) by plasma.
Particularly, in the parallel plate type plasma processing apparatus, a high frequency power is applied to at least one of an upper electrode and a lower electrode provided to face each other, a gas is excited into plasma by electric field energy of the high frequency power, and a microprocess is performed on a target object by the generated plasma. Such a parallel plate type plasma processing apparatus has been mainly used for performing, for example, an etching process.
In the parallel plate type plasma processing apparatus, a processing gas is introduced into a processing chamber in which the upper electrode and the lower electrode are provided. The high frequency power is applied to at least one of the electrodes to generate plasma of the processing gas and then, for example, an etching process is performed on the wafer.
When forming an etching hole by the etching process, a photoresist is used as an etching mask. The photoresist is negatively charged and electric charge is neutralized on an etching surface in an early stage of the etching process. If an aspect ratio is increased as the etching process is performed, positive ions are deposited on a bottom of the etching hole so that the etching surface becomes positively charged. Therefore, the positive ions greatly contributing to the etching may not straightly introduced by a repulsive force of the positive ions within the etching hole, so that a shape of the etching hole may be bent. Further, it becomes difficult, for the positive ions to reach the bottom of the etching hole, and, thus, an etching rate is decreased.
Therefore, in order to solve such problems, for example, Patent Document 1 suggests a method of performing a plasma process. That is, In Patent Document 1, a plasma process is performed by alternately ON/OFF controlling the application of a high frequency power to the electrode so that plasma is generated and dissipated alternately within a processing chamber. Further, a negative DC voltage is applied to the upper electrode such that an application voltage during a period when the application of the high frequency power is OFF is higher than an application voltage during a period when the application of the high frequency power is ON.
In accordance with this method, the negative DC voltage is applied during the period when the application of the high frequency power is OFF, so that more secondary electrons can be generated and introduced into the etching hole with great acceleration. Therefore, a lot of secondary electrons and negative ions can be supplied into a contact hole during the period when the application of the high frequency power is OFF. As a result, the positive electric charges within the contact hole can be neutralized. Thus, when a high frequency power supply is turned on to generate plasma, positive ions can be straightly introduced into the etching hole and the good etching process can be performed.
Patent Document 1: Japanese Patent Laid-open Publication No. 2010-219491
Recently, as semiconductor devices become miniaturized, it is necessary to form an etching hole having a high aspect ratio. When the etching hole having a high aspect ratio is formed, a negative DC voltage applied during a high frequency power-off period needs to be higher.
However, if a higher negative DC voltage is applied, abnormal electric discharge may occur at a vicinity of the upper electrode and reaction products generated by the abnormal electric discharge may fail on an upper surface of a wafer. Therefore, a production yield of a semiconductor device may be decreased. The abnormal electric discharge will be explained below.
FIG. 9 is a longitudinal cross sectional view schematically illustrating a conventional configuration of an upper electrode and its vicinity in a plasma processing apparatus configured to perform the above-described etching process. As depicted in FIG. 9, an upper electrode 200 includes an electrode plate 201 provided to face a wafer and an electrode supporting member 202 configured to support the electrode plate 201. The electrode plate 201 is made of a semiconductor such as silicon, and the electrode supporting member 202 is made of a conductor such as aluminum. Above the electrode supporting member 202, a grounding member 204 made of a conductor is provided to face the electrode supporting member 202 in parallel with each other via a cylindrical insulating member 203. Within the electrode supporting member 202, there is provided a gas diffusion room 211 communicating with gas supply openings 210 formed at the electrode prate 201. A processing gas is supplied into the gas diffusion room 211 through a gas flow path 212 formed within the insulating member 203. A DC power supply 220 is electrically connected to the upper electrode 200 and the grounding member 204 such that the upper electrode 200 is a negative pole and the grounding member 204 is a positive pole.
Conventionally, in this plasma processing apparatus, a negative DC voltage of, for example, about 300 V is applied to the upper electrode 200. Although there is no problem in this case, the present inventor has found that when the negative DC voltage to be applied is increased to, for example, about 1200 V in order to further accelerate secondary electrons and ions, electric discharge occurs between the electrode supporting member 202 constituting the upper electrode 200 as the negative pole and the grounding member 204 as the positive pole via the gas flow path 212. Therefore, there is required a method for preventing electric discharge from occurring even when a higher DC voltage is applied as compared to a conventional case.